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cpu:atomic

文書の過去の版を表示しています。


CPU Atomic / Memory Barrier

fetch_add (seq_cst)

x64

; linux clang x64
lock xaddl   %esi, 8(%rsp)
; windows x64
lock xadd   dword ptr [rbp-10h],edx

ARMv7A

	dmb	ish
.LBB0_1:
	ldrex	r0, [r4]
	add	r1, r0, #1
	strex	r0, r1, [r4]
	cmp	r0, #0
	bne	.LBB0_1
	dmb	ish

ARMv8.0A

.LBB0_1:
	ldaxr	w9, [x8]
	add	w1, w9, #1
	stlxr	w9, w1, [x8]
	cbnz	w9, .LBB0_1

ARMv8.2A

	ldaddal	w23, w8, [x22]

fetch_and (seq_cst)

x64

	movl	(%rsp), %ecx
	movl	%ecx, %edx
	andl	$4, %edx
	movl	%ecx, %eax
	lock	cmpxchgl	%edx, (%rsp)
	movl	%eax, %ecx

ARMv8.2A

	ldclral	w21, w1, [x19]

fetch_or (seq_cst)

ARMv8.2A

	ldsetal	w20, w1, [x19]

fetch_xor (seq_cst)

ARMv8.2A

	ldeoral	w8, w1, [x19]

exchange (seq_cst)

ARMv8.2A

	swpal	w23, w1, [x19]

compare_exchange_weak (seq_cst)

x64

lock  cmpxchgl	%ecx, 8(%rsp)
lock cmpxchg dword ptr [rbp-10h],edi

ARMv7A

	ldrex	r2, [r4]
	cmp	r2, #0
	beq	.LBB0_18
	clrex
	b	.LBB0_19
.LBB0_18:
	dmb	ish
	mov	r0, #3
	strex	r1, r0, [r4]
	cmp	r1, #0

ARMv8.0A

	stlr	wzr, [x19]
	ldar	w1, [x19]
	adrp	x0, .L.str.11
	add	x0, x0, :lo12:.L.str.11
	bl	printf
	ldaxr	w2, [x19]
	cbz	w2, .LBB0_18
	clrex
	b	.LBB0_19
.LBB0_18:
	orr	w8, wzr, #0x3
	stlxr	w9, w8, [x19]
	cbz	w9, .LBB0_51
.LBB0_19:

ARMv8.2A

	casal	w2, w19, [x22]

compare_exchange_strong (seq_cst)

x64

lock  cmpxchgl	%ebx, 8(%rsp)
lock cmpxchg dword ptr [rbp-10h],r13d

ARMv7A

	ldrex	r2, [r4]
	cmp	r2, #3
	bne	.LBB0_24
	mov	r0, #0
	dmb	ish
.LBB0_22:
	strex	r1, r0, [r4]
	cmp	r1, #0
	beq	.LBB0_25
	ldrex	r2, [r4]
	cmp	r2, #3
	beq	.LBB0_22
.LBB0_24:
	clrex
	mov	r1, #0
	dmb	ish
	b	.LBB0_26
.LBB0_25:
	dmb	ish
	mov	r1, #1
.LBB0_26:

ARMv8.0A

.LBB0_21:
	ldaxr	w2, [x19]
	cmp	w2, #3
	b.ne	.LBB0_24
	stlxr	w8, wzr, [x19]
	cbnz	w8, .LBB0_21
	orr	w1, wzr, #0x1
	b	.LBB0_25
.LBB0_24:
	clrex
	mov	w1, wzr
.LBB0_25:

ARMv8.2A

	casal	w2, wzr, [x22]

load

ARMv8.xA (seq_cst/acquire)

	ldar	w1, [x19]

ARMv8.xA (relaxed)

	ldr	w1, [sp, #8]
cpu/atomic.1562426578.txt.gz · 最終更新: 2019/07/07 00:22 by oga