cpu:atomic
文書の過去の版を表示しています。
目次
CPU Atomic / Memory Barrier
fetch_add (seq_cst)
x64
; linux clang x64 lock xaddl %esi, 8(%rsp)
; windows x64 lock xadd dword ptr [rbp-10h],edx
ARMv7A
dmb ish .LBB0_1: ldrex r0, [r4] add r1, r0, #1 strex r0, r1, [r4] cmp r0, #0 bne .LBB0_1 dmb ish
ARMv8.0A
.LBB0_1: ldaxr w9, [x8] add w1, w9, #1 stlxr w9, w1, [x8] cbnz w9, .LBB0_1
ARMv8.2A
ldaddal w23, w8, [x22]
compare_exchange_weak (seq_cst)
x64
lock cmpxchgl %ecx, 8(%rsp)
lock cmpxchg dword ptr [rbp-10h],edi
ARMv7A
ldrex r2, [r4] cmp r2, #0 beq .LBB0_18 clrex b .LBB0_19 .LBB0_18: dmb ish mov r0, #3 strex r1, r0, [r4] cmp r1, #0 ~
ARMv8.0A
stlr wzr, [x19] ldar w1, [x19] adrp x0, .L.str.11 add x0, x0, :lo12:.L.str.11 bl printf ldaxr w2, [x19] cbz w2, .LBB0_18 clrex b .LBB0_19 .LBB0_18: orr w8, wzr, #0x3 stlxr w9, w8, [x19] cbz w9, .LBB0_51 .LBB0_19:
ARMv8.2A
casal w2, w19, [x22]
cpu/atomic.1562412342.txt.gz · 最終更新: 2019/07/06 20:25 by oga