差分

このページの2つのバージョン間の差分を表示します。

--- cpu:atomic [2019/07/06 20:23] – oga
+++ cpu:atomic [2019/07/07 21:08] (現在) – [x64 (relaxed/release/seq_cst)] oga
@@ 行 44: / 行 44: @@
-==== ARMv8.2A ====
+==== ARMv8.1A ====
 <code asm>
@@ 行 51: / 行 51: @@
+----
+===== fetch_and (seq_cst) =====
+==== x64 ====
+<code asm>
+; linux clang
+	movl	(%rsp), %ecx
+	movl	%ecx, %edx
+	andl	$4, %edx
+	movl	%ecx, %eax
+	lock	cmpxchgl	%edx, (%rsp)
+	movl	%eax, %ecx
+</code>
+<code asm>
+; windows
+prefetchw   [rbp-10h]
+mov         eax,dword ptr [rbp-10h]
+nop
+mov         ecx,eax
+and         ecx,4
+lock cmpxchg dword ptr [rbp-10h],ecx
+</code>
+==== ARMv8.1A ====
+<code asm>
+	ldclral	w21, w1, [x19]
+</code>
+----
+===== fetch_or (seq_cst) =====
+==== ARMv8.1A ====
+<code asm>
+	ldsetal	w20, w1, [x19]
+</code>
+----
+===== fetch_xor (seq_cst) =====
+==== ARMv8.1A ====
+<code asm>
+	ldeoral	w8, w1, [x19]
+</code>
+----
+===== exchange (seq_cst) =====
+==== x64 ====
+<code asm>
+; linux clang
+	xchgl	%esi, (%rsp)
+</code>
+<code asm>
+; windows
+xchg        edx,dword ptr [rbp-10h]
+</code>
+==== ARMv8.1A ====
+<code asm>
+	swpal	w23, w1, [x19]
+</code>
+----
 ===== compare_exchange_weak (seq_cst) =====
@@ 行 66: / 行 149: @@
 ==== ARMv7A ====
+<code asm>
+	ldrex	r2, [r4]
+	cmp	r2, #0
+	beq	.LBB0_44
+	clrex
+	b	.LBB0_45
+.LBB0_44:
+	dmb	ish
+	mov	r0, #3
+	strex	r1, r0, [r4]
+	cmp	r1, #0
+	beq	.LBB0_53
+.LBB0_45:
+</code>
+==== ARMv8.0A ====
+<code asm>
+	ldaxr	w2, [x19]
+	cbz	w2, .LBB0_18
+	clrex
+	b	.LBB0_19
+.LBB0_18:
+	orr	w8, wzr, #0x3
+	stlxr	w9, w8, [x19]
+	cbz	w9, .LBB0_51
+.LBB0_19:
+</code>
+==== ARMv8.1A ====
+<code asm>
+	casal	w2, w19, [x22]
+</code>
+----
+===== compare_exchange_strong (seq_cst) =====
+==== x64 ====
+<code asm>
+lock  cmpxchgl	%ebx, 8(%rsp)
+</code>
+<code asm>
+lock cmpxchg dword ptr [rbp-10h],r13d
+</code>
+==== ARMv7A ====
+<code asm>
+.LBB0_47:
+	ldrex	r2, [r4]
+	cmp	r2, #3
+	bne	.LBB0_50
+	strex	r1, r0, [r4]
+	cmp	r1, #0
+	bne	.LBB0_47
+	dmb	ish
+	mov	r1, #1
+	b	.LBB0_51
+.LBB0_50:
+	clrex
+	mov	r1, #0
+	dmb	ish
+.LBB0_51:
+</code>
+==== ARMv8.0A ====
+<code asm>
+.LBB0_21:
+	ldaxr	w2, [x19]
+	cmp	w2, #3
+	b.ne	.LBB0_24
+	stlxr	w8, wzr, [x19]
+	cbnz	w8, .LBB0_21
+	orr	w1, wzr, #0x1
+	b	.LBB0_25
+.LBB0_24:
+	clrex
+	mov	w1, wzr
+.LBB0_25:
+</code>
+==== ARMv8.1A ====
+<code asm>
+	casal	w2, wzr, [x22]
+</code>
+----
+===== load =====
+==== x64 (relaxed/acquire/consume/seq_cst) ====
+<code asm>
+	movl	(%rbx), %esi
+</code>
+==== ARMv7A (relaxed) ====
+<code asm>
+        ldr    r0, [r4]
+</code>
+==== ARMv7A (acquire/consume/seq_cst) ====
+<code asm>
+        ldr    r0, [r4]
+        dmb    ish
+</code>
+==== ARMv8.xA (relaxed) ====
+<code asm>
+	ldr	w1, [x19]
+</code>
+==== ARMv8.xA (acquire/consume/seq_cst) ====
+<code asm>
+	ldar	w1, [x19]
+</code>
+----
+===== store =====
+==== x64 (relaxed/release) ====
+<code asm>
+	movl	%ebp, (%rbx)
+</code>
+==== x64 (seq_cst) ====
+<code asm>
+	xchgl	%ebp, (%rbx)
+</code>
+==== ARMv7A (relaxed) ====
+<code asm>
+        str     r5, [r4]
+</code>
+==== ARMv7A (release) ====
+<code asm>
+        dmb     ish
+        str     r5, [r4]
+</code>
+==== ARMv7A (seq_cst) ====
+<code asm>
+        dmb     ish
+        str     r5, [r4]
+        dmb     ish
+</code>
+==== ARMv8.xA (relaxed) ====
+<code asm>
+        str     w20, [x19]
+</code>
+==== ARMv8.xA (release/seq_cst) ====
+<code asm>
+        stlr    w20, [x19]
+</code>